Trait kernel::hil::spi::SpiMasterDevice
source · pub trait SpiMasterDevice<'a> {
// Required methods
fn set_client(&self, client: &'a dyn SpiMasterClient);
fn configure(
&self,
cpol: ClockPolarity,
cpal: ClockPhase,
rate: u32
) -> Result<(), ErrorCode>;
fn read_write_bytes(
&self,
write_buffer: &'static mut [u8],
read_buffer: Option<&'static mut [u8]>,
len: usize
) -> Result<(), (ErrorCode, &'static mut [u8], Option<&'static mut [u8]>)>;
fn set_rate(&self, rate: u32) -> Result<(), ErrorCode>;
fn get_rate(&self) -> u32;
fn set_polarity(&self, polarity: ClockPolarity) -> Result<(), ErrorCode>;
fn get_polarity(&self) -> ClockPolarity;
fn set_phase(&self, phase: ClockPhase) -> Result<(), ErrorCode>;
fn get_phase(&self) -> ClockPhase;
}
Expand description
SPIMasterDevice provides a chip-select-specific interface to the SPI Master hardware, such that a client cannot changethe chip select line.
Required Methods§
sourcefn set_client(&self, client: &'a dyn SpiMasterClient)
fn set_client(&self, client: &'a dyn SpiMasterClient)
Set the callback for read_write operations.
sourcefn configure(
&self,
cpol: ClockPolarity,
cpal: ClockPhase,
rate: u32
) -> Result<(), ErrorCode>
fn configure( &self, cpol: ClockPolarity, cpal: ClockPhase, rate: u32 ) -> Result<(), ErrorCode>
Configure the bus for this chip select.
sourcefn read_write_bytes(
&self,
write_buffer: &'static mut [u8],
read_buffer: Option<&'static mut [u8]>,
len: usize
) -> Result<(), (ErrorCode, &'static mut [u8], Option<&'static mut [u8]>)>
fn read_write_bytes( &self, write_buffer: &'static mut [u8], read_buffer: Option<&'static mut [u8]>, len: usize ) -> Result<(), (ErrorCode, &'static mut [u8], Option<&'static mut [u8]>)>
Perform an asynchronous read/write operation, whose
completion is signaled by invoking SpiMasterClient on
the client. Write-only operations may pass None
for
read_buffer
, while read-write operations pass Some
for read_buffer
.
If read_buffer
is None
, the
number of bytes written will be the mimumum of the length of
write_buffer
and the len
argument. If read_buffer
is Some
, the number of bytes read/written will be the
minimum of the len
argument, the length of write_buffer
,
and the length of read_buffer
.
If read_write_bytes
returns Ok(())
, the operation will be
attempted and a callback will be called. If it returns Err
,
no callback will be called and the buffers are returned.
- Ok(()): the operation will be attempted and the callback will be called.
- Err(OFF): the SPI bus is powered down.
- Err(INVAL): length is 0
- Err(BUSY): the SPI bus is busy with a prior
read_write_bytes
operation whose callback hasn’t been called yet.
sourcefn set_rate(&self, rate: u32) -> Result<(), ErrorCode>
fn set_rate(&self, rate: u32) -> Result<(), ErrorCode>
Set the clock/data rate for this chip select. Return values:
- Ok(): set successfully. Note actual rate may differ, check with get_rate.
- Err(INVAL): a rate outside the bounds of the bus was passed
- Err(BUSY): the SPI bus is busy with a read_write_bytes operation whose callback hasn’t been called yet.
- Err(FAIL): other failure
sourcefn set_polarity(&self, polarity: ClockPolarity) -> Result<(), ErrorCode>
fn set_polarity(&self, polarity: ClockPolarity) -> Result<(), ErrorCode>
Set the bus polarity (whether idle is high or low) for this chip select. Return values:
- Ok(()): the polarity was set.
- Err(BUSY): the SPI bus is busy with a
read_write_bytes
operation whose callback hasn’t been called yet. - Err(FAIL): other failure
sourcefn get_polarity(&self) -> ClockPolarity
fn get_polarity(&self) -> ClockPolarity
Return the current bus polarity.
sourcefn set_phase(&self, phase: ClockPhase) -> Result<(), ErrorCode>
fn set_phase(&self, phase: ClockPhase) -> Result<(), ErrorCode>
Set the bus phase for this chip select (whether data is sent/received on leading or trailing edges).
- Ok(()): the phase was set.
- Err(BUSY): the SPI bus is busy with a
read_write_bytes
operation whose callback hasn’t been called yet. - Err(FAIL): other failure
sourcefn get_phase(&self) -> ClockPhase
fn get_phase(&self) -> ClockPhase
Get the current bus phase for the current chip select.